As semiconductor devices have become more highly integrated, a channel length (i.e., the distance between a source region and a drain region of the MOS field effect transistor) may be reduced. The reduction of the channel length may cause short channel effects. Methods of forming source/drain regions including an LDD (lightly doped drain) structure have been proposed in order to reduce/prevent short channel effects. However, these methods may not be as effective when a line width of a gate electrode is less than 0.1 μm. Korean Laid-Open patent No. 2000-041698, Japanese patent No. H9-045904, Korea Laid-Open patent No. 2000-056248, discuss techniques for forming a buried insulation region under the channel region to suppress short channel effects.
FIG. 1 is a perspective view and FIG. 2 is a cross-sectional view illustrating a conventional MOSFET including a buried insulation region. Referring to FIG. 1, insulation patterns 20 are formed on a predetermined region of the semiconductor substrate 10. The insulation patterns 20 are formed in a region of the substrate that will be under a gate of the MOSFET, to help reduce a short channel effects.
An epitaxial layer 30 is formed on the semiconductor substrate 10 using epitaxial growth. The epitaxial layer 30 is formed to have a thickness thicker than that of the insulation pattern 20. Therefore, as shown in the drawing, the epitaxial layer 30 is also formed on the insulation pattern 20. After the epitaxial layer 30 and the semiconductor substrate 10 are sequentially patterned to form a trench to define an active region, a device isolation pattern 40 is formed in the trench.
The insulating pattern 20 is formed of an amorphous material, such as oxide and nitride, which causes the epitaxial layer 30 to be grown in separate portions (or individually) from the underlying substrate 10 around the insulating pattern 20. The separate portions of the epitaxial layer 30 meet above the insulating pattern 20 to form a discontinuous boundary 35 (or seam) in the epitaxial layer 30 in a region that is to be the channel region of the MOSFET.
Referring to FIG. 2, a gate insulation layer 50 and a gate pattern 60 are formed sequentially on the epitaxial layer 30. Source/drain regions 70 are formed in the epitaxial layer 30 on both sides of the gate pattern 60. The portion of the epitaxial layer 30 including the seam under the gate pattern 60 (i.e., between the source/drain regions) is used as the channel region of the MOSFET. The discontinuous boundary 35 in the epitaxial layer 30 may adversely affect the electrical characteristics of the MOSFET. In view of the above, the conventional techniques discussed above using the insulation pattern 20 may suppress short channel effects, but may also degrade electrical characteristics of the MOSFET.